| Substructure method as a degree of freedom reduction method is very suitable for solving large-scale structure and has been obtained widely application. In a substructure analysis, the whole structure is divided into several smaller independent parts. For each small part the degree of freedom of which is condensed into a substructure in the next step. Therefore, the total degree of freedom in the whole structure can be reduced by assembly of the condensed substructures. Each substructure is then calculated after the assembled structure is solved. The substructure method has great advantage in solving the complicate problem with large number of degrees of freedom.In general, electronic package includes board level, component level and wafer level. The modeling and simulation for solder joint reliability of an IC package is a typical multiple scale problem. The package model used for simulation has often been simplified to reduce the scale challenge. Some the lower-order components such as trace and UBM are generally ignored. However for some critical reliability problem, it is necessary for modeling the details of local components by conducting multiple scale finite element analysis. For example solder joints of an IC package should be meshed in a reasonable way in a drop test. Although more and more papers have been seen in the drop test study, there are still a large number of degree of freedoms on their FEA model that needs a large amount of CPU time, while the substructure method has high efficiency and can greatly save the CPU time. Currently we have not yet seen the research papers that use the substructure method to solve the drop test reliability problem. Therefore it is necessary to develop the substructure method for the study of the solder joint reliability.Solder joint reliability in thermal cycling is a steady-state problem and it could be simulated with static substructure method. In this paper, the solder joints are divided into two groups according to analysis with unit temperature load. Non-critical solder joint was condensed by performing static substructure method. To ensure the accuracy, the range of the temperature cycle is divided into five phases, and the solder joints are condensed at 6 different temperatures. Simulation results showed that in the case of just condensing non-critical solder ball into substructures, with substructure method the elements is about 11% less than with regular nonlinear method. However with substructure method, it can save 35% of CPU time than with the regular fully nonlinear method.Drop test is an important method for solder joint reliability analysis. To follow JEDEC standards for drop simulation, it would result in a very large model by including drop table into modeling. Therefore, many research studies have proposed methodologies that only include drop test board and chip in modeling and simulation. Large Mass Method, Direct Acceleration Method and Input—D Method are introduced in drop test simulation in this paper.In this thesis, the efficiency of the three methods is compared and it is found that Direct Acceleration Method and Input—D Method induced about similar CPU time for same model but Large Mass Method will take longer time. The chips on board would not damage at the same time in finite drop. Large number of studies show that the chip closed to the JEDEC board bolt location (U1) is the easiest damage part. To study the solders at U1, three substructure method are proposed according to above mentioned three methods. Efficiency of three substructure method is studied by compare CPU time with the same solution model. Similar with conclusion mentioned above, results show that substructure analysis with Large Mass Method takes longer CPU time while the other two dynamic substructure methods take similar solution time. It should be noticed that substructure analysis with Input—D Method has a little fewer CPU time than with Direct Acceleration Method. Comparing three substructure analysis with three normal solution methods, it is found that the elements in substructure analysis is one-seventh of normal solution model and CPU time is one-third with the three normal methods.Input—D Method with substructure analysis is taken to study solder joint reliability. According to simulation results, the solder joints close to screws are most likely to fracture and the fracture surface is at the bottom of joint that attached to trace. The location of the most easy-to-failure is found in the chip under the surface. The larger the chip thickness the larger the stress generated in solder joints for drop test. Stress in solder joints decreases with solder joint size but increases with the pitch. |
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