A Study Of Realizing Gaussian Random Number Based On Ovcdm

Varieties of noises exist in the communication system, which make negative ef-fect to the system. In the communication system, it usually needs analyze its perfor-mance with the noise interference. As one of the most common noise, Gaussian noise is often used to simulate the communication system. What's more, using the statisti-cal property of Gaussian noise, it can simulate other communication channel perfor-mance after some relative transformation. Thus, designing a simple construction and high quality Gaussian noise generator is necessary for theoretical researching and practical work of communication system simulation.OVCDM (Overlapped Code Division Multiplexing) technology is the next gen-eration wideband wireless communication network construction technology which invented by professor LiDaoben. In this OVCDM system, the correlation of its code can be regarded as constraint relation instead of interference. All the interferences come from extraneous noises such as Gaussian noise.Gaussian noise is a random number sequence with Gaussian distribution in es-sence. Generating Gaussian noise is actually getting a random number sequence which satisfies Gaussian distribution. Numerical methods for researching Gaussian random number sequence generation at present, mainly base on mathematical method. While it generates the pseudo random number sequence using these methods, it can be viewed as the true random number sequence within limit and can be used for sim-ulation of communication system or other engineer applications.This paper introduces the fundamental principle of OVCDM technology at first; simulates the system based on this technology over AWGN channel. On this base, generates the Gaussian random number sequence and realizes the hardware imple-mentation. Considering the fact of the project, it adopts the method of uniform ran-dom number by Box-Muller algorithm transformation. On the base of analyzing uni-form random number algorithms, a classical linear congruential method is adopted.On Gaussian random number hardware implementation, the design cycle can be greatly shortened by using ISE Design Suite 10.1 and AccelDSP of Xilinx the new FPGA design tools. The implementation on the Xilinx Virtex-5 xc5vsx50t FPGA oc-cupies 2378 slices and 2 block RAM and its maximum clock frequency is 47.6MHz. It saves much resource for other module designing of system.