Low-noise Ldo Linear Regulator Design

The power management IC(integrated circuit) has the many advantages,such as high integrity,high price ratio,the most simple outer circle circuit,the best capability, the high-efficiency power supply etc.At present,many aboard companies still mostly occupy the market of power management IC.It has important significance to research and development of domestic power management IC.And it has much great importance to require such a big market.Therefore,it is of great importance to study the LDO linear regulator circuit.The object of this paper is to design a low noise(LDO) linear buck regulator.It adopt 0.5 um CMOS technology,which has the wide input voltage range(2.5V—5.5V).The output voltage is 1.8 V.The output noise is less than or equal to 30uV(rms). This circuit is primarily used to power supply of the circuit such as CPU,DSP etc.In addition,it also designs the thermal shutdown and current limit sub-block,which guarantee the electric circuit working in safe operation area(SOA).During circuit designing,the basic theory of LDO linear buck regulator is given first.Then the general structure of the IC is designed based on its function requirement.And then designs the sub-block circuits in details.Applying Cadence, simulations of the sub-block circuits and whole chip,and giving the reasonable electric circuit data.The results indicate that the IC has achieved their function object and numeric object.