Rs (255,223) Decoder Fpga Implementation And Performance Testing

Error-control coding technology is very important to reduce error probability and improve dependability in satellite communication. RS (Reed-Solomon) code is an excellent linear cyclic block code in the error-control field. It has been widely used in deep space exploration for its powerful random and burst error-correction ability, and has been adopted by NASA, ESA and CCSDS as recommended standard. RS encoding data transportation, using a RS(255,223) hardware encoder, has been adapted in our "DOUBLE STAR"exploration plan. Because of the complexity of RS hardware decoder, software decoding was used in the ground receiving system which can not guarantee real time communication. A high speed hardware RS decoder is necessary in our future projects. Having studied several kinds of RS decode algorithm, we have chosen the reformulated inversionless BM algorithm to solve the key equation of the decoder. Parallel multiplier of finite field based on composite basis and divider using exponential subtraction have been developed. By implementing the above presented approaches, not only the decoder's speed is improved but also the decoding latency and hardware overheads are reduced. Other two important tasks of our research project include the design of the verification system and the performance test for the decoder. We have set up a test system based on PCI bus for the testing of the decoder. After verified the test system's reliability with 41 grades m sequence random data produced by hardware, the speed, decoding latency, error-correction ability and other performance parameters of RS decoder were tested comprehensively. In the testing process, coding blocks are disturbed according to different bit-error probability of BPSK system to test the error-correcting ability of the RS decoder. The RS decoder, composed of only 180,000 gates, is realized on a XILINX FPGA (XCV600E-6HQ240C). The test results have proved that, the decoder has a...