The Application Of FPGA In The Electrostatic Precipitator

The main work of this paper is to research and development to the programmablecontroller as the core FPGA electrostatic precipitator control system, its design is not onlysuitable for electrostatic precipitator power supply control system upgrading, transformation,and is suitable for different industries and the condition of production process control.Elaborated the electrostatic dust removing technology at home and abroad to develop thecurrent situation, elaborated the existing implementation advantages and disadvantages, putforward with high speed, high integration and high reliability FPGA as the core of thecontroller device, the use of VHDL hardware description language to realize the link controlfunction. Using VHDL language to compile the system. For electrostatic precipitator and thevarious parts of the program, using QuartusII software for simulation, and record thewaveform simulation, and then download to module, realizes the hardware verification.Through a controllable silicon voltage regulating unit, L-C steady flow unit, step-uprectifier circuit, A/D conversion unit, the watchdog design, realizes the high voltage powersupply automatic voltage, to the inside of the system to provide the maximum average coronapower, stability, enhancing the efficiency of dust.Operating voltage signal, after ADC0809sampling control and conversion, into theFPGA prepared by the comparator and counter, realize the system every minute overvoltage4times to produce an alarm signal, at the same time, cut off the power, realizes the high voltagepower supply overvoltage protection, the compiler and simulation results meet the designrequirements of dust control.Design uses a144pin EP1C3T144C8FPGA chip, realized the high voltage power supplyof electric precipitator, alarm protection, fan5minutes delay time and40min,20S rappingrapping period, with high voltage follower ash, fire sprinkler control function of each part ofthe compiler and simulation test, verify the relevant VHDL compiler correctness, hasachieved the anticipated target.