| Phase-Locked Loop (PLL) has been widely used in frequency synthesizer and clock data recovery circuit worked as the aim of multiplying frequency and phase-lock. With the increase of the range of operating frequency, wider frequency range and shorter locking time are asked, thus we are facing great challenge in designing PLL. In this paper, an analysis of the characters of PLL, taking into account the frequency of reference clock and locking time, is provided in this paper. And then a dual-loop PLL is established that can achieve a wider range of operating frequency and fast-capture.A 200MHz PLL IP core on the basis of the research of PLL theory and the technology of capturing is designed in 0.18μm CMOS process. The layout post simulation shows that it works well, and it can achieve fast-capture with 20MHz~50MHz reference clock. The major research work and invention of this paper is includeing as follows:1. Researching the main theories of PLL, especially the technology of fast-capture. This work can be the base of researching PLL further.2. Building a dual-loop PLL, according to the aim of the wide tuning range and fast-capture. One loop is used to coarsely tuning the frequency of output, and the other one is used to accurately tune, In this way, PLL can lock phase faster.3. Innovating a Voltage-Controlled Oscillator circuit which can be programmed to change the number of VCO delay cells. So the VCO can select the parameter of KVCO and work in different operation frequency ranges that make VCO work at centre voltage more stably.4. Improving general frequency detector to adjust to programmable VCO. So PLL can choose different delay cell combination by adjusting the ratio between the frequency of reference clock and the feedback of clock. In this way, PLL can capture phase more quickly.5. this paper has designed a PLL chip based on 0.18μm technology and compared it to convention PLL with single delay cell ring. The result proves that the lock-time decrease to 50%. |
PDF Full Text Request