Design For Soft Error Tolerant And Low Power Of FSM

With the wide spread application of deep submicron technology, the size of integrated circuit has been rapidly decreased, together with continuing decreased working voltage and increased working frequency. When encounter the circuit bombardment, ICs would become more sensitive to neutrons andαparticles in packet materials. The increasing of working frequency and ICs density also consumes more and more power. Therefore, the design for low power and soft error tolerant controller become increasingly urgent. In this dissertation, we research on the design for soft error tolerant and low power of FSM by introducing state probability. The main work is showed as follows.(1) On the side of soft error tolerant design, we start with the state probability. Firstly, introduce some knowledge about Markov chain. Then, make a model to calculate the state probability. Based on Markov chain model, a redundancy state selection method was proposed. Compared with the original circuit, this approach can improve the protective quality (SEU) by 87.6% on average. It not only helps reduce the soft error rate tolerant, but this method, compared with the traditional TMR program, greatly saves the overhead of circuit area.(2) On the low power coding design, our research is started with the discussion of algorithm, namely, called state machine coding algorithm, which we have further revised. As to the deficiency of the speed in convergence rate of FSM state encoding according to traditional genetic algorithm (GA), we posed a algorithm for low power state encoding, based on estimation of distribution algorithms. To accelerate the constringency speed of the encoding algorithm, we use the estimation of distribution algorithms; establish the model for learning probability and state probability. Compared with GA, this approach can reduce 3% power on average and save 31.6% time for encoding.(3) Based on the first two programs, we have especially posed a design method for both soft error tolerant and low power consumption. In the fault-tolerant, we use the circuit state probability model, by strengthening the high probability state to reduce the probability of soft errors occurring on the risk. In the low power consumption, the use of low-power state encoding based on the probability of the same state machine to split the state machine as a starting point, aiming to achieve low power consumption. This method obviously helps to reduce the power consumption of circuit overhead.