Verification Of Queue Scheduling Algorithm Based On VMM

With the rapid growth of the scale of integrated circuit, the complexity grows rapidly too. The issue of design verification becomes one of key issues in chip design. In ten million-gated ASIC, reusable IP and SoC design, verification costs 70 percent of the whole design effort.This paper firstly present elementary theory of verification, VMM platform related technologies and the process of building verification environment based on VMM. And then, analysis and compare all kinds of common queue scheduling algorithms,design a scheduler model with three level and mixed queue scheduling algorithms using verilog language. With this scheduler model as design under test, put forward a verification strategy which is inserting monitor between two level of the scheduler to realize hierarchical verification, and a method of checking scheduled results statistically. And then, the process of building verification environment based on VMM, which contain all of the structure of components and connection to each other, is explained significantly. In order to ensure sufficient verification, construct enough test cases aimed at covering all the features of the design. The verification results indicate: line coverage reach at 98%, condition coverage 91%, state machine coverage 100%. All those indicate that the verification strategy and method put forward in this paper are common for verifying scheduler, and also are highly flexible,efficient,and reusable.