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Design Of Adaptive Post Deblocking Filter Based On FPGA

Posted on:2011-11-26Degree:MasterType:Thesis
Country:ChinaCandidate:D TianFull Text:PDF
GTID:2178360308463562Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Most video compression coding standards, such as H.264, MPEG-4 and AVS, are based on the block discrete cosine transform (BDCT) compression. In these coding standards, each small block is seperately quantized and encoded which ingore the relevance between adjacent blocks. Therefore, blocking effect occurs on the boundary of the block in the decoded image.A post-processing deblocking filter based on image enhancement is designed comprising of two processes, mode decision and filtering. Based on the deblocking filter in MPEG-4 appen dix, some improvements are made as follows. 1.change the mode deci sion method based on the block no longer on each row and column, which greatly reduce the computation of mode decision,2. use the shift 8×8 blocks, which comprise both vertical and horizontal boundary in the center of the block and avoid frequent reading and complicate filtering sequence control, further reduce the running time,3. use a blocking effect detection method based on difference between neighborhood boundary pixel, and filtering in this paper are all implemented by shift with no multiply and divide. MATLAB simulation results show this deblocking algorithm based on offset and shift reduce the computation time and the hardware structure, and increase the processing speed.In hardware implementaion, timing and frame storage of video data is the key. Because of the large data, we use DDR SDRAM as the memory in image processing system. When processing in each DCT unit, in order to improve the efficiency of the read and write in DDR SDRAM, we present a pretreatment frame storage strategy. A raster scan to DCT block format transformation is added before storing. Then the output data can be got in accordance with the consecutive address, which greatly inrease the access speed of DDR SDRAM.The overall system verification of the de-blocking system is implemented with Xilinx Video starter kit as the target device The input signal is got from S-video signal interface of the DVD, the output after de-blocking system is put into S-video signal interface of television. Validation results show that de-blocking filter system can get a stable video with less blocking effects and the subjective visual quality is improved.
Keywords/Search Tags:post-processing de-blocking, activity calculation, adaptive filtering, FPGA
PDF Full Text Request
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