Research On High Reliable Transmission Control Algorithm For Air & Space Information Network

With the development of modern information technology, Air & Space Information Networks, known as the most promising high technology, show great advantages in terms of large capacity and time efficiency. Thus it leads to a variety of applications such as military guidance, space surveillance and so forth.In Air & Space Information Networks, due to its special location in the air, it requires the strong robustness of the communication protocol between the terminal and access equipment. Therefore, the design of an access protocol is needed, which could support the QoS, so as to make sure that the data transmission can be processed with high speed and high reliability. For this requirement, the scenarios and the characteristics of the Air & Space Information Networks are analyzed first in this thesis. And then we propose an algorithm called Extended Fast Recovery for Throughput Enhancement (EFRTE) which is able to obtain high speed and high reliability. In EFRTE, because of joint usages of piggyback and accumulated acknowledgement, together with the optimized packet scheduling and retransmission, the overall performance is excellent, which can adapt to the channel changes.Then a three-stage model and the corresponding numerical results are given in this thesis to testify the performance of EFRTE. At the same time, the specific OPNET simulation is used as well. Both the theoretical and simulation results demonstrate that EFRTE can coordinate with high-speed physical layer communications, build the reliable data link between the source and the destination. Hence EFRTE can reach high throughput, small latency and low jitter in Air & Space Information Networks.In the end, the key parameters from theoretical and simulation results are applied to the real FPGA platform. To guarantee the reliable physical layer communication, high-speed interface (SFP) is tested firstly. Afterwards, EFRTE is implemented in various modules. The final demo test results demonstrate that the implementation of EFRTE is feasible on the FPGA platform, which can obtain point-to-point reliable data transmission.