Research Of The Highly Effective Hardware Implementation For FEISTEL Structure Encryption/decryption Algorithm

The modern cryptography is classified into symmetric key and non-symmetric key cryptography according to the type of encryption key. The advantage of the symmetric key cryptography is the high speed and easy to implemented because using the same key when encryption and decryption. The Feistel structure is the most widely used structure among symmetric key cryptography algorithms.This thesis takes the research of the highly effective hardware implementation for Feistel structure by example of two typical Feistel structure algorithms. Propose a general hardware IP solution supporting configurable registers which can be accessed by AHB bus. Optimize the internal algorithm core by using area-reducing and low-power methodology such as retiming, reuse, and operation isolation.This thesis proposes several solutions to meet the requirements for different application. Every solution is evaluated including area, critical path, required cycles, data throughput rate and power. Final result indicated that compared with other hardware implementations, the solutions proposed in this thesis have performance strengths, can be applied at the currently mainstream real-time occasions.