With the speech recognition technology ever-changing, speech recognition has been gradually applied to every aspect of business prodution and human life. This tendency calls for speech signal procssing to meet more strict technology demand on accuracy, real-time processing and performance of hardware.Distributed Speech Recognition(DSR) proposed an effective solution to reduce the computational burden at the front-end of the system. So in recent years, the DSR system has attracted more and more attention.Based on the research of the DSR system, using digital processing advantage of the Altera's new-generation programmable logic devices, this thesis proposes a FPGA-based front-end system architecture.There are four primary parts of the work in this paper:(1) Base on deliberate analysis on algorithm in DSR system and comparison between different designs, the architecture in hardware system of speech feature extraction has been explored particularly.(2) According to the statistic result of many speech samples and numerical simulation based on Matlab, the width of fixed point in speech characteristic parameter, which is the basis for the system design, has been determined.(3) This thesis proposed a new system architecture based on the existing methods, including three functional modules, computation of the auto-correlation function, realization of Levinson-Durbin recursion algorithm and computation of LPCC(Linear Predication Cepstum Coefficient). Finally, consequent hardware implementation project and detail analysis are presented. (4) Adopting Alter FPGA Cyclone EP1C20 chip to test, emulate and validate the system, observing the output of the results by logic analyzer SignalTap II. Hardware simulation is compared with Matlab modeling results using Matlab.Final results show that, this system can extract the LPCC coefficients of speech signal in a shorter cycle, with data error in an acceptable range, which can be used as the front-end of DSR system. |