System Design, FPGA Validation And Physical Implementation Of Speech Recognition System

Speech recognition is widely used in the non-contact control system. Most of the traditional speech recognition systems are based on the personal computer, which is too large to be carried away easily and also too power-consumimg and expensive to be widely used. In order to solve these problems, a speaker-dependent isolated word speech recognition chip is designed by this thesis.Firstly, speech recognition algorithm is studied and improved in order to be easily converted into a hardware system. Based on that, module participation and interface definition are implemented. Then RTL coding is done for several modules and the whole RTL system is also integrated. Finally, the RTL system for speech recognition is completed after several months'RTL simulation and debugging. The speech recognition's RTL system designed by this thesis has exactly the same simulation results compared with the speech recognition's software system.Then RTL code optimization is done in order to reduce power and be easily implemented for the physical design, and the synthesis results show that area and power are both smaller than the version without RTL code optimization. FPGA validation platform is also setup for this speech recognition system so that more people's speeches can be testted. The FPGA validation results shows that the speech recognition rate can achieve an average of 91% when 5 reference speeches are stored.With a blance of timing, area and power, logic synthesis is done in order to convert this speech recognition's RTL system into a technology depended and physical implementary netlist, which is under the support of HHNEC 0.35μm EEPROM technology. Physical implementation is also done for this speech recognition system by Floorplan, Place, CTS, Routing and DFM optimization.At last, Back-end verifications like Formal verification, parasitic extraction and Static Timing Analysis, post-simulation, DRC and LVS verification are all implemented for the back_end design of speech recognition system to ensure that it has no Functional, Timing, DRV, DRC and LVS violations. The recognition rate of the speech recognition chip designed in this thesis can achieve an average of 91% and passed all the backend verification. The chip's core utilization is 63% and total power dissipation is 20.93mw with an area of 2094 x 4598μm2. The chip can works at the speed of 9MHz, which can meet the at-speed requirement of the 8KHz original voice input.