Research And Logic Implementation Of 100GE PCS Layer MLD Mechanism Based On IEEE802.3ba

Until the end of April 2010, the demand of the higher speed data transfer in broadband service is tremendously increased even the final standard for 40G/100G Ethernet IEEE802.3ba has not been formally released. The leading companies and organizations are actively involved in the standard drafting of the IEEE802.3ba. As the capability of the logical-units improved by the chip vendors, the research and development possibility for the 40G/100G Ethernet equipments has been achieved.Based on the study of IEEE P802.3ba/D2.0 draft and the 802.3ba related conference documents, here is done the in-depth research of 100G Ethernet physical layer architecture and the mechanism of PCS Multi-Lane Distribution, offered the design of multi-lane which is compatible of 10*10G,4*25G and 5*20G optical modules.The logical implementation part is designed for pre-researching. According to IEEE802.3ba standard, for MLD&CAUI program in 100GE interface technology, PCS-MLD model in 100G Ethernet physical layer has been designed by VerilogHDL, implemented by Virer-5LX330T FPGA chip of Xilinx. Time-sequence simulation has been done for all functional modules under the top-level module of data up-down routing by Modelsim 6.2se. Synthesis, Map, download file generating is done by Xilinx ISE9.2 for the top-level module.Combined with the 100GE prototype pre-research project, using the professional data source generator and test apparatus, researched on the 100GE prototype on site and also did real tests on the PSC-MLD model.This study has great reference value on the research of the 40G/100G high-speed Ethernet as well as for the design of the network equipments.