Design And Efficient Hardware Implementation Of Onboard Satellite Image Compression System

In this paper, an efficient implementation of image compression system for satellite in a programmable hardware is proposed. According to the requirements of satellite onboard image compression system such as compression ratio, reconstructed image quality, process ability, power consumption and reliability, a fast SPIHT(set partitioning in hierarchical trees) algorithm is present. In the last part, a real-time satellite image encoder based on lifting wavelet transform and fast SPIHT algorithm is implemented with two FPGAs to achieve image coding and system control respectively.Various methods of image compression algorithm are analyzed and compared in this paper, and we select SPIHT algorithm to implement because of its low complexity and high performance. Design scheme and verification plan of the hardware system are also provided. The system mainly consists of a Xilinx FPGA and an Actel FPGA, and two groups of input data with a bit-rate of 256Mbps can be processed in real time. The compression ratio, the output mode and the operation parameters of the system are also configurable and could be accessed by a CPU bus. The design can meet the technical requirements in the aspect of performance, complexity and reliability, etc.