High Speed Parallel Bus -DDR Interface Noise And Timing Analysis

With the integration of integrated circuits, the system clock speed of the continuous improvement, high-speed circuit interconnection relations have not be regarded as a lumped parameter, but has become a transmission line with distributed parameters. This makes it appear in high speed integrated circuit delay, reflection, attenuation, scattering, crosstalk and noise issues, resulting in signal distortion, timing confusion, data errors and system errors trigger other serious consequences. This integrated circuit interconnect and packaging systems posed a severe challenge, high-performance integrated circuit chip to match demand with high-density and high reliability of the interconnection and packaging technology.For DDR, because its based on the parallel bus structure, and therefore more vulnerable to interference from adjacent signals, and with the DDR interface, the operating frequency and transmission rate of increase, the signal between the noise and timing problems will become even more serious. From DDR1 to DDR3, DDR interface, the constant-voltage noise margin decreases leading to further reduce the clock cycles further reduced. This makes the signal quality of the DDR system design, interface timing, noise and other requirements have become more sophisticated, more stringent. Chip, package, and PCB design veneer face tremendous challenges, and even restrictions on DDR gradually become a bottleneck to further improve transmission rates.In order to ensure the normal operation of DDR chip, to avoid the signal quality problems, this article DDR chip, packaging, single-board interconnects as a whole, through the optimization of the overall performance to improve DDR. First of all pairs of DDR chip layout design, noise and optimize the DDR timing; carefully selected package type, laminated, and size; through a single network simulation to determine, DDR chip topology and matching, as well as PCB trace length of the veneer; the use of Cadence, Ansoft simulation software and other EDA vendors on-chip electromagnetic simulation model building, and through Hspice simulation of the circuit built-end chip, through the multi-network SSN simulation, analysis, and determine the chip noise, timing of the reasons for that; combination of simulation results, routing and timing of the chip layout put forward specific requirements, packaging and PCB design veneer width, line spacing, and lines of equal length the extent of specific binding.Through the thesis research work, making DDR2-400MHz chip design to a successful development, greatly shorten the development cycle, reduce development costs, while eliminating noise, timing and other signal quality problems. As at the beginning of the design on the right chip, package, single board co-simulation carried out to ensure a successful overall system timing margin also make the system large, in order to improve the follow-up provided a good foundation. However, pressure to make the final adoption of DDR2 ran 512MHz, the higher frequency of DDR for the future design of a good reference for.