Research On Key Technologies Of Accelerator For Biological Sequence Analysis

Biological sequence analysis is one of the bases of bioinformatics research which has great value. As the biological sequence database increasing rapidly, the demand to data processing capability is becoming higher, and the support of high-performance computing is needed urgently. Dynamically reconfigurable system constructed with FPGA is one of the means of studying high-performance computing, which give effective provide to bioinformatics research.Sequence comparative analysis and sequence assembly are important parts of the biological sequence analysis. The key technologies of accelerator for their applications were studied in this paper. To sequence comparative analysis, pair alignment, bio-sequence searching, multiple sequences alignment were studied, and Smith-Waterman algorithm, ClustalW program, Phrap program were token as their examples respectively. Kinds of solutions were involved, such as sending two sequences to PE array synchronous, put intermediate results into external memory, multiple seeds detect in parallel, expanding multiply, and so on. Contrasting to software, the accelerators can achieve speed up more than 1555, 27, 24 respectively.Phrap program was studied in this paper which was taken as an example of the sequence assembly. The feature of the program was analysed, the core function was accelerated with hardware. The simplified index was used to decrease the number of reads to alignment, systolic array was introduced to find the matches of reads, match areas were aligned in two-way. Contrasting to software, the accelerator can achieve speed up of 3.5.The design of hardware data structures and the technologies of optimizing storage which were used by biological sequence analysis were studied in this paper. The stack, queue, list, tree, graph were analyzed separately, the structures suited to their applications were made, and the optimized storage structure was designed.The study to prototype building was also made in this paper. Accelerators can be implemented in this prototype perfectly. The structure of dynamic reconfigurable system was designed. The design of high-speed I/O channel PCI Express and the control technology of high-speed high-capacity external memory DDR2 SDRAM were studied and implement in the prototype.