The Design And Analyze For Parallel Processing Fault-Tolerance On-Board Computer

Space technology has great efect on the human civilization and development. The on-board computer system is an important part of the satellite, which software and hardware must have the high dependability and real-time. In this thesis,we have designed a parallel processing On-Board computer system of four-CPU based on COTS technique. This system using RTEMS and processor with SPARC V8 architecture as its software-hardware platform, have the functions of parallel computing based on message passing, state monitoring and self-configuration, data exchange and distribute, software re-injection, and ect.In this thesis, we study the key technologies of the on-board computer system, analysed the Fautl-Tolerance architecture carefully. Fault-Tolerance policies based on these research have been established for these policies was put forward. we focus on some characteristic practical Fault-Tolerance technique, such as software re-injection, slave reboot ,energy limit programme,etc. We generalize the combinatorial reliability model for 3 different architectures and conpare the reliability of them,base on the introduction of reliability terms and analysis of computer system performance and dependabillity models. At last, summarized and analysed the problems during development, we looked forward to the prospect.