Design And Implementation Of RS Encoder And Decoder Based On Multimedia Communication Satellite

RS code has excellent capability in correcting bursting errors. RS code can remarkably improve the reliability in communications of multimedia satellite when it interleaves and concatenates with Viterbi as outer code. Now, many communication standards adopt the concatenated codes of RS and Viterbi. For satisfying the requirement of multimedia satellite, we have studied the algorithm of RS encoding- decoding, the technique of RS interleaves and concatenates with Viterbi, and also we have completed the optimization design and realization of encoder-decoder. Main work and efforts in this thesis are listed as follows.1. Thoughtful analysis of RS encoding and decoding algorithms. After comparing BM Algorithm with Euclid's Algorithm at complexity, we get the first is better. We have studied Forney Algorithm, a implementation method has been proposed after analyzing the complexity of inverse operation in Forney Algorithm.2. Optimization design and realization of RS(244,212) encoder. Based on studied the theory of low complexity bit parallel architectures for polynomial multiplication over GF( 28 ), a high speed, low device utilization general multiplier and fixed multiplier have been designed and realized. The circuit of encoder has been given. Besides, an improved circuit structure of the encoder has been proposed. On this basis, we have designed and implemented a RS(244,212) encoder in Verilog HDL. The synthesized resources utilization of the encoder is 285 slices in Xilinx ISE 9.1i Vertex2p, and the maximum throughput can be achieved 2.0Gbps.3. Optimization design and realization of RS(244,212) decoder. The circuit of syndrome module, key equation module, error-location and error-value module have been given. The key equation module completes a multiply operation by two-step multiplication. Therefore, nearly half of the general multiplier is reduced. After analyzing the timing of three modules, we have proposed three-stage pipeline for RS decoder. Based on this method, we have designed and realized a RS(244,212) decoder in Verilog HDL. The maximum throughput can be achieved 1.4Gbps, and the synthesized resources utilization is 1832 slices in Xilinx ISE 9.1i Vertex2p.4. Study and design of RS interleaves and concatenates with Viterbi. We have studied the concatenated codes, and have analyzed the benefit of adding interleaving in the concatenated codes. Comparing with several interleaving matrix in experiments, we get an optimal interleaving matrix which is 128×61 matrix. On this basis, we have designed and implemented an Interleaved-Concatenated-Codes which is accords with the TDM carrier communication system standard of user link in multimedia communication satellite.