Study The Method Of The Hardware Implementation Of The Arithmetic For Smoothing Process Of Digital Images

In the process of digital images, especially the one of the application in smoothing, median filtering has become an arithmetic which is more and more significant. In this paper, a novel quick arithmetic of median filtering will be presented, which is the optimized version of the general purpose median filtering of bubble sorting. This paper will give the hardware implementation of this quick arithmetic on FPGA, and it will deal with the process of a real time image signal from the camera. At last a comparison between the real time image signal before and after process will be given.The quick arithmetic of median filtering presented in this paper is more compact and have bigger advantage in timing compared with the one of general purpose bubble sorting, and it can save a lot both in timing and area. In this paper, the verification process of this quick arithmetic will also be given.In this paper, the whole system of the hardware platform of this median filtering quick arithmetic is based on the building of the Aquila-C18X5 FPGA board. The following chips are included in this develop board: SAA1075 video coding chip form PHILIPS; TVP5150 video decoding chip from TI and the SPARTAN3A DSP chip from Xilinx. The operation procedure of the whole system is based on that the real time image signal from the camera, and then, which will be passed to the DSP chip though the process of the video coding chip, will be output to the VGA though the process of the video decoding chip. During building the hardware system, we need to create an I2C interface, which can configure the registers for both the video coding and decoding chips. In this paper, we will pay attention to introducing the design and debugging procedure of the I2C module in the architecture of the hardware system.