| Achieving reliable communication approaching Shannon's capacity limit at effective power cost is the ultimate object of modern channel coding technique. The invention and development of low-density parity-check codes (LDPC) narrow the gap between real system performance and channel capacity. Since their rediscovery, design, construction, decoding, analysis and applications of LDPC coded have become focal points of research. In this paper, mainly on the LDPC code decoding algorithm and ASIC implementation to achieve more in-depth studies.Several iterative message passing algorithms for LDPC codes, such as Gallager's Bit Flipping (BF) algorithm, Belief Propagation (BP) algorithm and Min-sum algorithm etc, are considered in this thesis. The principles of coding and decoding algorithm for LDPC codes are systematically summarized and the equations for updating messages in sum-product algorithm are also derived. Algorithm for ASIC implementation provides a theoretical basis.Eventually, the architectures for the hardware implementation of LDPC decoder, including full parallel architecture, serial architecture and partly parallel architecture, have been analyzed. Elaborated the ASIC structure based on fundamental matrix's min-sum algorithm. Additionally, based on national standard (GB), Framing Structure, Channel Coding and Modulation for Digital Television Terrestrial Broadcasting System, we proposed the ASIC structure of VNU and CNU via 0.6 rates. |
