H.264 Hardware Encoding Research And Implementation Of Integer Transform And Quantization

H.264 is the new generation of video coding standard. The new standard has characters such as low bit rate, high quality picture, strong error fix ability and network adaptive ability. It will be used in video conference, video on demand, digital TV and handheld device. Because H.264 is the new video coding standard, the selection and implementation of the algorithm has not been well optimized. There are a lot of job has to be done to improve the performance of the H.264 coder and decoder. The research of the critical algorithm and its implementation in H.264 coder and decoder is very helpful for the application of this new standard.Due to its' higher complexity, H.264 algorithm is very difficult to be applied in real-time environment, and real-time HD video encoding is hardly achieved through software approach. In this paper, complexity of H.264 coding is analyzed, and computation distribution is added up, results of which indicate that Inter-frame Prediction and Integer Transform Quantification occupy a large number of coding cycles. In order to achieve real-time encoding, the implementation of H.264 encoder in FPGA is studied. For high-definition video in real-time encoding, a hardware encoding system with Multibus SoPC is proposed, and functions of hardware and software of this system is partitioned apart. According to the characteristics of H.264 hardware encoding system, soft-core function module has been divided, employing pipeline technology. On this basis, H.264 hardware encoding system based on PowerPC 405 embedded processor is constructed, and the smallest PowerPC 405 system is carried out in the Virtex-II Pro FPGA implementation.Finally, this article will implement the H.264 Integer Transform and Quantization module. The result of the synthesis and performance indicates that the integer transform and quantization in H.264 is fast and well parallelized. The hardware implementation of the integer transform and quantization given in this research can achieve low cost, low power, while retaining performance requirements.The research methodology and achievements in this thesis can be reference to future hardware design for H.264 hardware encoder.