A Dynamic Thread Scheduling Model For Heterogeneous Mpcore Based On Configurable Processor

Cause of needs for high performance, more and more organizations pay attention to heterogeneous multi-core architecture. Task scheduling is a key part of this kind of system.This paper proposes a novel thread level dynamic scheduling model for heterogeneous multi-core architecture which consists of configurable processors. All core share a common ISA (instruction set) and are separately extended with a set of new instructions for speeding up application processing. Via the relationships between cores, ISAs and threads, this model is able to dynamically assign a thread to a core which supports the ISA that thread used.Furthermore, this paper implements the model based on Mutek operating system and parallelizes Motion-JPEG decoder as test application. According to target and control experiments result, this model can raise performance by 31% compared to static scheduling in the same environment. This model can achieve 91.6% performance of All-extended SMP, which is the most powerful architecture, but only use 55.6% of chip area. Besides, compared to the reference paper result, this model can acquire higher speed with less chip area.This model can make better trade-off between speed and chip area than former models. And it also simplifies the programming model since it works on POSIX thread model.