Research Of H.264 HD Encoding On CELL

As the development of internet and digital video, the requirement of real-time encoding is much more. High definition and quality video applications becomes more important. But the huge computation complexity goes beyond the conventional x86 processor's capability. As the physical constrains limit the increasing of chip's frequency, it's hard to increase the frequency more. So we pay much attention to parallel calculation to continue Moore's Law. Parallel architecture brings a great challenge in software design, as it requires the programmer to think in parallel. The previous software always designed without taking parallel working in mind, so most of them have to be changed to fit parallel architecture. Multi-core and parallel calculation will bring a renovation in software design and algorithm design.CELL is a multi-core processor with high parallel calculation ability. This thesis studies parallel calculation's infection on video compression. Using CELL as hardware platform, this thesis implements a high definition encoder on CELL. It achieves real time encoder's requirement by using eight cores together. Then a new DCT-domain distortion estimation model is proposed to accurately estimate each macroblock's PSNR. In addition, a MB-level quality control algorithm is proposed to improve the MB's quality fluctuation using this distortion model.In this thesis, CELL's architecture is introduced at first, some parallel programming thinking and considerations are proposed. Then the methods of implementing and optimizing a H.264 encoder on CELL's Synergistic Processor Element (SPE) are introduced. In our research, we find that previous motion estimation and mode decision algorithms can't achieve ideal performance on SPE. In order to explore the data level parallelism in CELL's parallel technique, this paper introduces a new fast motion estimation algorithm, which can achieve much better prediction accuracy and lower computational complexity compared with Diamond Search (DS) algorithm. We also optimize the mode judgment of inter and intra, and the intra part can be reduced from 11% to 3%. We can get a real time SD encoder on a single SPE by these methods.To implement a real-time HD encoder on CELL, we first implement a real time SD encoder on a single SPU by optimizing Motion Estimation algorithm, DMA transfers etc. We analyze parallelism in H.264 encoder and propose three multi-core parallel encoding methods on CELL. Then we improve the one of the methods by a dynamic load assignment algorithm. In this way, we can get a real time HD H.264 encoder by using eight SPEs.For many applications like video surveillance and digital cinema, it is desirable to encode video content with constant video quality. However, although constant quantization parameter is used in video encoder, quality fluctuation in macroblock level is still very large and standard deviation of PSNR is typically about 1.8dB. Since distortion is introduced in the process of quantization of DCT coefficients, we propose a new DCT-domain distortion model which utilizes the truncated tailing bits in quantization to estimate distortion in macroblock level, and QP of each block is determined by the estimated PSNR. Experimental results show that our proposed model can accurately estimate distortion of each MB before implementing quantization and the corresponding RMSE is only about 0.3dB (less than 1% of the actual value). Compared with previous works, our proposed algorithm can achieve 0.57dB enhancement in quality stabilization.