| RFID(Radio Frequency Idetification) is a kind of non-touching automatic identifying technology. It can identify moving or quiet objects utilizing the space-coupling induction principle ofalternative magnetic and/or electronic field. It has many promising features such as large information capacity, long effective distance and multiple tags operation and is widely used in access control, logistics and other management area. RFID has become a common and important research and development area all over the world.The work of this paper can be divided into two parts. First, the RFID system based on ISO/IEC18000-6 Type B protocol is discussed, the baseband digital signals processing module of the RFID reader is designed based on FPGA. In the design, it follows the principle of modularization and structured programming. The program language is Verilog HDL. The design of hardware contains main controller state machine, CRC error detection module, FM0 decoder, CRC coder and error detection module, Manchester coder, FIFO, UART and so on. This paper proposes a Single-Chip solution of the digital logic part of the RFID reader based on ISO/IEC18000-6 protocol. It is provided with faster processing rate, simpler circuitry and stronger transformability. The baseband transmission rate is 40 kbps.The anti-collision algorithms, which is one of key technologies,is also discussed. This paper compares and analyzes lots of algorithm; include ALOHA algorithm, Slotted ALOHA algorithm, Dynamic Slotted ALOHA algorithm and Binary tree algrithm. Every kind of algorithm performance as well as their suitable situation are concluded on the basis of the comparison and analyse. The system model of Slotted ALOHA algorithm and Binary tree algrithm based on FPGAs are also provided. These designs have advantage in reilability and modularization, and can be redveloped easily. It carries on the simulation to these two modules of algorithm. The results of the simulation indicate that this design is stable, reliable. |
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