Research On High Performance Packet Classification Based On FPGA

With the continuous development of the Internet, the Internet Service Providers hope that networks can provide more and better services, such as Qos, firewall, VPN, etc. Although there are many kinds of the services, all of these services require the routers can classify the packets, and the corresponding technology of rule lookup is Packet Classification.This paper introduces some existing algorithms, and then we put forward a high-speed algorithm for packet classification which bases on HiCuts(Hierarchical Intelligent Cuttings) and RFC(Recursive flow classification), and suits to implement by FPGA. Under the condition of limited space, we also provide an optimized method for building tree according to the rules' characteristic. Furthermore, we design two parallel methods to improve the lookup efficiency, which are pipeline and mater-slave. The experimental result shows that it's much ascendant than HiCuts in space under the same condition, and the speed of classification can arrive at 3Mpps. Last, we part the complex system into several sub-modules and design their functions. We also design the hardware architecture which is implemented by FPGA.