Research Of Key Technologies In VQ Based Video Compression

Video compression always is the key technology in the video processing field. As the development of multimedia and network, the requirement for the real-time video compression enhances at the same time. Vector Quantization (VQ) is a simple and effective algorithm which has simple architecture and easy implementation, and it also has high processing speed, therefore, it is very appropriate for real-time video compression application. Motion Estimation (ME) is another video coding technology which attempts to effectively use the temporal redundancy between successive frames. Therefore, if VQ and ME are combined in video coding algorithm, it will keeps the image performance and also has high compression ratio in implementation.Firstly, in the infra-frame coding, a vector quantization (VQ) algorithm based on rotating compressed codebook and its implementation is proposed. The algorithm compresses the original codebook by taking advantage of the original codebook directional correlation, and resumes the original codebook by rotating in the encoding. Compare with the typical vector quantization algorithm, the algorithm decreases 75% memory room and 75% I/O bandwidth but lost only 0.28dB PSNR.Secondly, in motion estimation algorithms, a low-power full search motion estimation unit is proposed. And some fast motion estimation algorithms, such as diagonal matching and diamond search algorithm, are disused in the paper, and the implementations also are designed.Thirdly, the project team has developed a PDVQ chip with PDVQ algorithm, therefore, based on the existent research foundation, a PDVQ based video coding system is proposed. The system can increase the speed and reduce the I/O bandwidth, and also can increase the compression ratio while keeping the reconstructed image quality.Finally, the architecture presented in this paper has been described in Verilog RTL code and synthesized by Synopsys Design Compiler with Charter 0.35um standard cell library, and the result of gate-level simulation is correct. For verify the function, all the designs are downloaded into FPGA, and the waveform in the logic analyzer also is right.