Algorithm Study On Microarchitectural Floorplanning

With fabrication technology entering deep submicron era, microprocessor designs in current semiconductor technologies are already interconnect -limited, and interconnect latency and power consumption have been predicted to have a larger impact in future technologies.With the design of the system involved many constraints, the space of the design are increased dramatically.As the initial stage of layout, floorplanning has a marked impact with the chip's performance. Efficient floorplanning algorithm is very important.In this thesis,it presents multi-objective microarchitecture level floorplanning algorithm for designing high-performance,high-reliability microprocessors.The contributions of this thesis are as follows:For the factor of chip's temperature,through reading,tracking lots of new papers, it has in-depth understood the latest development of the thermal in the design of integrated circuits,also have known some optimization algorithm.Based on Hotspot,it has proposed a streamlined interconnect delay model.With the impact of the delay cycle,we also presented multi-objective microarchitecture level floorplanning algorithm for designing high-performance, high-reliability microprocessors. it simultaneously considered both performance and temperature objectives such that our automated floorplanner can provide a balanced or goaldirected processor organization that achieves both optimized objectives.In this thesis, it tries to handle the smooth optimization of the conflicting objectives of performance and thermal effects. It presents a floorplanning optimizer that consists of two steps.Unlike the previous works which integrating the two objectives straightforward, we analysis the pipelining design in micoarchitectural designs and take advantage of the slacks along each path so that the floorplanner can be guided to optimize the thermal effect without degrading the performance too much. By using two-stage optimization, we can effectively reduce the peak temperature while maintaining high performance.In this thesis,it applies the floorplanning algorithm in the design of microprocessor system.It provided an verification tools for physical design and has achieved certain results for the fioorplanning of the microprocessors performance optimization. It also has opened up a new field of study. With the wide range of physical design and architecture microprocessor design, there are many subjects needed to be researched. With the development of integrated circuit technology designed,it can promote the development of the microprocessor.