Application Of FPGA-based Digital Logic System In Distributed Polarization Coupling Analyzer

Distributed polarization coupling analyzer (DPCA) is an effective testing tool in manufacture and application of polarization maintaining fibers (PMFs). It can be used for the detection of distributed polarization mode coupling along the fiber. Thus, the performance of optical fiber polarization devices and systems can be improved. It cam also used in the fields such as optical fiber gyroscopes and distributed sensing.Based on the previous work in the design of optics and mechanics, field programmable gate array (FPGA) -based data acquisition system of the DPCA is designed. And the control of the DPCA modules, such as analogue to digital conversion (ADC) conversion module, step motor driver modules, etc. are accomplished.The major achievements in this thesis are:The principle, structure and application of the DPCA are presented and data that the analyzer needs to acquire are analyzed, including polarization coupling positions and coupling coefficient.FPGA-based digital logic design methodologies are introduced.The circuit of distributed polarization coupling analyzer is designed. Data acquisition card function and modules are presented.The (universal serial bus) USB bus interface hardware circuit and firmware based on Cypress Corporation's USB driver CYCY7C68013 are accomplished.The core control software and hardware are designed based on Altera Corporation's FPGA EP2C8Q208C8 using very high-speed hardware description language (VHDL) and high performance electronic design automation (EDA) platform Altera QuartusII5.0. All FPGA design steps are accomplished, including modules, coding, functional/ timing simulating, logic synthesis, and analyzing, program download and hardware verification.The concepts of transmission line and signal integrity in high-speed digital design and the principle about printed circuit board (PCB) layout design incorporating FPGA and USB drivers are presented; PCB layout of data acquisition card is accomplished.Data acquisition card debugging is accomplished. Temporal simulation, timing analysis and hardware verification results are presented.