Design Of Underwater Video Data Compression System Based On FPGA

In recent years,the extending connotation and the expanding function of the ocean exploitation and national defence technology have created a new space of application and development for the underwater detection and signal processing.Visual detection technology as an effectively supporting of underwater non-acoustic detection was recived broad attention.The advances in autonomous underwater vehicle(AUV) and underwater communication technology have promoted a surge of research in the field of underwater video.Effective data storage and data transmission in acoustic or radio channel were the basis of visual detection. Due to the limited bandwidth of acoustic channel and storage space for video data, underwater video compression technology became the key to underwater visual detection. Because of the better time-frequency localization and multiresolution analysis, wavelet transform was widely used in image compression. Because lifting wavelet transformation does not rely on the Fourier transformation , it can complete the wavelet transformation in the space region, and is more suitable for the characteristic of hardware achievement.With the need of underwater visual detection, this dissertation compares and demonstrates in detail the design and achievement scheme of the underwater video compression encoder in this paper, Finally, FPGA chip is chosen as the hardware developing platform for the project, and SOPC technology is used to conduct cooperative designing of software and hardware, so as to meet the demand of high speed processing and flexibility, and meet the general availability. The paper first analyses the characteristic of underwater video image, and the specific property of the acoustic channel transmission, the collection of video image, introduces basic theory of Wavelet transformation, and the selection of compression algorithm at first, then builds the system of compression against Minor Wavelet algorithm.The paper's first important research content is how to capture and store the video data stream real time by FPGA. Including: the video signal collection, storage, DMA controller design and Software programming.The paper's second important research content is the relizing of lifting wavelet coding by FPGA,design with Altera DSP Builder . Including:the IP core design of color space transformation,lifting wavelet coding ,code-book generation and software programming.Finally, characteristics of this system are summarized based on the actual result of the research and development of this system, and the future designing work is also prospected.