The Research And Design Of GPS Receiver Baseband Processor

In recent years, since the extensive application of Global Positioning System (GPS) in navigation, measurement, communication, civil engineering, entironment, tourism and other areas, the research of GPS receiver has become hot research topic at present. There are many kinds of GPS receiver, such as single-freqeuncy (L1 band) C/A code receiver, dual-frequency (L1 band & L2 band) receiver, and GPS/GLONASS dual-system compatible receiver and USA military receiver. The signal-freqeuncy (L1 band) C/A code receiver is most extensively used, which was the study object of this paper.Single-freqeuncy (L1 band) C/A code receiver is composed by RF circuits, baseband processor and navigation calculation. The core parts of this kind of GPS receiver baseband processor—signal acquisition, tracking and bit-synchronization, were investigated in this paper. According to static receiver, the range of acquisition were that Doppler frequency shift's range was from (-5 kHz+IF) to (5 kHz+IF) and C/A code phase shift's range was from 0 bit to 1023 bit.The component of GPS, the principle of GPS receiver—direct spread spectrum communication, signal structure and characteristic of GPS, were introduced in this paper, the character of C/A code was validated and the threshold which was needed in bit-synchronization is calculated using MATLAB, the design method of hardware GPS receiver's signal acquisition, tracking and bit-synchronization was proposed. The Verilog HDL design was used in the design.Acquisition algorithm in time domain and in frequency domain was compared in the paper, and the acquisition block was achived by using the former. The tracking cell was implemented by using the coupling of code tracking loop and carrier wave tracking loop, while the code tracking loop and frequency carrier tracking loop were completed by DDL and COSTAS PLL respectively, the bit- synchronization was also designed. All the design was implemented in the FPGA based on Xilinx Spatan 3E XC3S500E and was based on the global sampling clk, whose frequency was 6.25MHz. In the paper, the frequency accuracy of carrier wave was 500 Hz, and the phase accuracy of C/A code was an interval between two sampling dots in acquisition block. The frequency accuracy of carrier wave was frequency resolution of Numerically Controlled Oscillator (NCO), and the phase accuracy of C/A code was an interval between two sampling dots in tracking cell.In order to save the space of memory, the local C/A code generator based on RAM, NCO based on CORDIC algorithm and the code phase detector based on Robertson approximate algorithm were proposed in this paper.Finally, the GPS L1 IF digital signal was simulated by using the structure of GPS signal, this signal was used to confirm the accuracy of the design of acquisition, tracking and bit-synchronization. Then some basic cells were configured in the FPGA based on Xilinx Spatan 3E XC3S500E, and validated by using timing simulation and debugging on the board based on Chipscope Pro.