Device Optimization And Process Yield Improvement Of 0.15UM High Speed Logic

In the recent years, more and more electrical products have higher speed, higher density and lower price, especially PC related products, such as CPU,graphic card and so on. With the development of these products, the operation speed and function need to be improved continuously. At the same time, the power's consumption and price of single IC chip also need to be reduced. For these special applications, we must optimize the IC manufacture process and device performance. Then high speed logic device arises.According to high operation speed of this kind of logic circuit, more advanced technology than 0.18um is mainly applied. As the last generation of using AL as back-end metal interconnection material, 0.15um manufacture technology has many advantages, such as low manufacture cost, high density, high speed and so on. So, 0.15um high speed logic process has higher application value and market foreground.Based on 0.15um basic logic process, current 0.15um high speed logic process is formed through computer process simulation to mainly adjust poly gate length, implant dosage and thermal budget. But there are still some issues that need to be solved. For example, device electrical parameters have some problems need to be optimized, and low product yield need to be improved.Due to these backgrounds, this paper is aimed to optimize 0.15um high speed logic circuit device and process performance to improve product yield. To realize these tasks, we adjust process parameters through theory analysis and experiment validation. For example, we modify the implant dosage and back end inter-metal-dielectric HDPCVD recipe and so on.Firstly, there are two major issues of device electrical parameters. One is the electrical parameters mismatch of horizontal and vertical device. The other is that NMOS off statues current is too high. So according to the comparison result between current process and 0.15um basic logic process, we find the mismatch of horizontal and vertical device is due to the shadow effect in LDD implantation process. We adjust the ion implant recipe from one rotation step to four steps during implant process to solve the device mismatch issue. For the second problem, we adjust implant dosage of LDD and Pocket steps. At the same time, we also adjust the parameters of back end interconnection to change the wafer stress. As the result of these actions, we reduce NMOS off statues current successfully.After these actions, yield has been improved to about 40%, but still doesn't match the criteria of mass production. We also optimize back end process. It mainly includes HDP deposition parameters of isolation layers and so on. All these actions help us to improve yield from 40% to 70%.Finally, we realize to optimize 0.15um high speed logic device and improve product yield. Mass production line is setup successfully.