Research About TCP/IP Offloading Technology In High Speed Ethernet

This thesis raises a point of that the development of high-speed Ethernet encountered bottlenecks, and addresses the design of TCP/IP Offload Engine (TOE) hardware module which can be used in an SOC system.This thesis addresses the design of a TCP/IP hardware module which can be used in an SOC system or an enhanced Network Interface Controller. The present implementation uses a state machine-based design which performs limited TCP/IP functions along with the required firmware for data movement and buffer management. There are several features of this design:1. Header processing modules for ARP, IP, ICMP, UDP, and TCP protocols are implemented in hardware.2. A bypass circuit is used to handle the IP header checksum and layer 4 checksum, including verification for receiving datagram and checksum calculation for transmitted datagram.However, at the time of write this thesis, the implementation is not fully accomplished. But the TOE architecture spec and management scheme are finished. The design of the whole Offload is made by the Altera UP3-IC6 Education Kit to test the Offload Engine.