System Architecture Of Equivalence Checking System Of Integrate Circuits And Implementation

With the continuous progress of IT, IC industry grows up quickly. While chip complexity is constantly increasing, the difficulty as well as the importance of functional verification of new product designs has been increased. The traditional methods, simulation and testing, hardly help designers to carry out a full design without errors. A very attractive and increasingly appealing alternative to simulation and testing is the approach of formal verification, which can provide this guarantee.The method of equivalence checking is the one that widely used and accepted in the verification of ICs, the fundemental aim of which is to verify the functional equivalence between two design models. From the view of the entire designation of digital systems, the problem of equivalence almost exists in each adjacent layers arranged in a top-bottom model. Besides, we can also utilize equivalence checking within one deifinite layer. During to the complicate and professional characteristic of digital systems and the certain requirements of IC designers, the construction of the system and core engine are two significant aspects to be solved as to fulfill a flexible, reliable and expandable system of equivalence checking.The thesis aims at the two problems advanced; it mainly discusses the architecture of the eqivalence system. After having a thorough research in the principles of equivalence checking, some efforts and discoveries of the architecture and the core engine were obtained. The main content of this paper:1. Detailed research on the fomal checking methods of IC designing2. Detailed study of basic principles of equivalence checking of ICs.3. The architecture of an EC system is presented based on SHELL engines.4. The principal algorithm of EC is well constructed based on ATPG...