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Preparation And Characterization Of The Epi-SOI Wafer

Posted on:2008-07-05Degree:MasterType:Thesis
Country:ChinaCandidate:Q F XiaFull Text:PDF
GTID:2178360212989107Subject:Materials Physics and Chemistry
Abstract/Summary:PDF Full Text Request
SOI (Silicon On Insulator) used for integrated circuit (IC) manufacturing has two advantages of increasing speed and reducing power consumption. SIMOX (Separate by Implant Oxygen) can be used to fabricate high-quality SOI wafers. However, the top-silicon layer of SIMOX-SOI wafers is very thin (typically 50~300 nm), which limits the application of such SOI wafers to a certain degree. Fortunately, this issue can be circumvented by the combination of epitaxy and SIMOX processes, which leads to so-called Epi-SOI wafers.In this thesis, the Epi-SOI wafers were prepared by ambient pressure chemical vapor deposition (APCVD) process on the SIMOX-SOI substrates. By means of preferential etching, the defects in the as-grown Epi-SOI wafers and the annealed ones were delineated. Moreover, the outdiffusion of oxygen from the buried silicon oxide (BOX) layer of SOI substrates was investigated. Listed below are the main results achieved in this thesis.1. The defects in the epi-layer of Epi-SOI wafer delineated by preferential etching manifest themselves as punch-through dislocations and dislocation pairs, which are originated from the SOI substrates.2. The dislocation density in the epi-layer of Epi-SOI wafer depends strongly on the SOI substrate. It was found that the dislocation density in Epi-SOI wafer using the SOI substrate with a 150 nm thick top-silicon layer was one order of magnitude higher than that in the Epi-SOI wafer using the SOI substrate with a 200 nm thick top-silicon layer.3. The high temperature annealing can be used to reduce the dislocation density in the Epi-SOI wafer. It was experimentally found the dislocation density in the Epi-SOI wafer was decreased to different degrees by the annealing at different temperatures in the range of 900~1200℃. It is preliminarily believed that during the high temperature annealing, the dislocations move to the epi-substrate interface and the edge of silicon wafer where they are annihilated and, moreover, the dislocations with opposite Burgers vectors will interact and thus ultimately being annihilated.4. The high temperature annealing of Epi-SOI wafer can lead to the outdiffusion of oxygen in the BOX layer of SOI substrate. Such an oxygen-outdiffusion becomes ever stronger with increased temperature in the 900~1100℃, while it is weakened at higher temperatures because the non-stoichiometric BOX layer actually acts as a sink for mobile oxygen atoms. This sink may enhance the in-diffusion of oxygen toward the BOX layer during high-temperature annealing.
Keywords/Search Tags:SOI, SIMOX, Epitaxy, Defects, SRP
PDF Full Text Request
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