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The Research Of Four Parallel Channel 2.5GPOS Linecard Output Strategy

Posted on:2007-05-13Degree:MasterType:Thesis
Country:ChinaCandidate:T QinFull Text:PDF
GTID:2178360212975696Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
People bring forward more requirements on routers processing ability, switching capacity and throughput as the fast development of Internet to higher speed and broader band.To research supports IPv4/v6, may expand to Terabit high performance router, including the system structure, the high speed connection, the large capacity switch networking, forword engine, the memory management and the queue scheduling and so on. Faced with the solution question is multichannel parallel POS/LAN/WAN high speed connection realization. The influential difficulty of 4×2.5GPOS linecard's realization mainly has: how to guarantee the system output efficiency under the high speed rate and the high density port condition; how to design the electric circuit under the current PCB craft's ultimate speed; how has its expansibility and so on several questions.This article unifies the national '863' Terabit router projects. From the output strategy, to analyze and summarize the existing output strategy good and bad points, proposed one kind of cell-channel divided output strategy (CCOS). Not only has carried on the simulation in the theoretical model foundation, and has produced in the corresponding line connection card project solution. Passed the test in the experimental environment and the system output efficiency has achieved 100%.The main content and innovation of this article as follows:Through establishing the model, to analysis and summarize its insufficiency of existing linecard output strategy. Then found out what needs to improve.To propose one kind of innovative and improved cell-channel divided output strategy (CCOS). Analyze its performance and carries on the simulation with the tool.To implement CCOS in Terabit router 4×2.5GPOS linecard sub-project, and make the first time application of Logic Lock methodology whitin designing the FPGA in engineering project, has solved the problem which the partial hardware resources is insufficient.
Keywords/Search Tags:Core Router, Output Strategy, Parallel, POS, Linecard, ON-OFF Model, Cell-Channel Divided Output Strategy, Logic Lock
PDF Full Text Request
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