CMOS Chip Design And Study Of Neural Recording And Signal Processing In Implantable Brain-Computer Interface

The fast development of information technology and life sciences has enabled it a global hot topic as well as research frontier that how to employ the microelectronics and integrated circuits (IC) technology to solve some common neural system related problems, e.g. paralysis, deafness, blindness. There are generally two aspects, neural recording and neural stimulation, for the Brain-Computer Interface (BCI) that connects the microelectronic device to the nervous system. This thesis mainly focuses on the recording techniques.In order to realize a realistic and chronically implantable BCI system, this work joins in the design of a full implantable device that will be formed by bonding the independent MEMS multielectrode-array (MEA) with the separately fabricated CMOS mixed-signal IC using bonding techniques such as Flip-Chip. After systematically analyzing the critical issues on the implantable BCI, this thesis presents the full custom design of a CMOS silicon chip for the hybrid device. The chip has been fabricated in UMC 0.18μm 1P6M twin-well CMOS process, containing a 16-channel 2:1 analog selector array, a low-power low-noise preamplifier-filter-buffer array, a 9:1 analog multiplexer and several digital control units. As for the most critical part, i.e. the preamplifier-filter-buffer array, we proposed a method of tuning the low-frequency cutoff using a digitally-controlled resistor-capacitor feedback, thus realizing switch between recording only the local field potentials (LFP) and recording both LFP and action potentials under 1-bit digital control. Symmetrical cascade diode-connected PMOS/BJT pseudo high-resistance resistors are employed in order to reach a very low cutoff frequency and provide DC offset rejection of beyond±1V due to the charge accumulation at the interface of electrode-electrolyte. Additionally, an improved analog multiplexer for multichannel neural signals has also been presented. The recording chip works with a dual power supply of±0.9V. Itprovides a mid-gain of 42.2dB, a upper-cutoff frequency of 12.4KHz and a tunable low-frequency cutoff of 1.98 Hz and 50.8Hz under 1-bit digital control, consuming a power dissipation of 12.66μW while occupies 0.045mm2 of silicon area with an input-referred noise of 4.1μVrms per channel. The results demonstrated high efficiency of the methods for this chip design.In the future, more components including spike sorting processor and RF transceiver should be integrated into the implantable device to build a closed-loop platform for the brain-computer bidirectional control. Such platform will be able to serve as a tool for neural prostheses and prediction of some neural diseases. Additionally, it will be significant to the neurobiology, physiology and brain research and will contribute to future frontiers of Neural Engineering research in China.