Research On The Still Image Compression Coder And Implementation Based On FPGA

Remote-sensing images have found wide applications in human life and military affairs, so the image coding technologies suitable for various requirements are of great practical significance. Embedded wavelet coding technique is a main method for image coding. Especially SPIHT (Set Partitioning in Hierarchical Trees) is one very important algorithms. Because of good restored image and random access for coding stream, these algorithms become the first choices in practice. With increasing requirements for image coding in many application fields, especially in military application aspects such as satellite surveillance etc, these excellent algorithms must be implemented in hardware urgently.In the still image coding field, the design of high performance image coder is always the goal that many relative researchers pursue. As for performance, low memory, low power and real time processing are hot points in research. In the paper, author studies the design of image coder in deep, especially places emphasizes on implemental architectures of coding algorithm with high efficiency and performance. The paper presents creatively implementation architectures with low computation and memory for real-time processing. The proposed architectures have been applied to real coding system successfully. To meet different application needs, the scheme also supports variable rate from 2 to 16 times compression without changing the hardware framework. The followings are main creative point of this paper:1. A VLSI architecture of line-based real-time lifting discrete wavelet transforms. The architecture processes horizontal filtering and vertical filtering simultaneously in 2-D transform using symmetry boundary. The transform time for one image equals to one image transmission time that is 2.6 times faster than traditional method. For reducing memory requirement, the architecture only uses and schedules internal buffer without external buffer.2. A bit plane-parallel architecture for a modified SPIHT algorithm using depth-first search bit stream processing. In the architecture, the coding information of each bit plane can be obtained simultaneously. The coefficient tree is traveled by depth-first search manner. The corresponding VLSI architecture to implement the formulated requirements is presented.