A Design Of Descrambler In QAM Demodulation Chip

Digital High Definition Television, as the third era Television Standard, has become the focus of contest in the countries all over the world. At present, Quadrature Amplitude Modulation(QAM) is a primary transmission mode for digital CATV signal. In order to disperse the transmitted signal energy and to ensure adequate binary transitions for clock recovery, the transmitted signal should be randomized.This paper focuses on the design of the descrambler circuitry and implementation in ASIC of DVB-C channel receiver.This paper concisely introduces QAM system in accord with DVB-C standard, and then the principles of descrambler and frame synchronization are illuminated. The design of the descrambler and the ASIC implementation are concretely introduced. The function modules mainly include four parts: parallel Pseudo-noise sequences generator, frame synchronization circuit, B8 HEX inverter and exclusive module. Each module's synthesis circuitries and simulated wave results are introduced. The simulation result indicates that the design meets the descrambler module demands of QAM demodulation syatem, and then the final ASIC implementation is described.