The Research Of CMOS Op-Amp Circuit-level Synthesis Method Based On IAGA

With the rapid growth of VLSI technology, the design of ASIC moves towards the integration of whole system into a single chip, which commonly includes both digital and analog circuits. Nowadays, digital units in such chips can be synthesized rapidly and reliably by HDL-based logic synthesis tool. In contrast, analog part is still required to be designed manually by experienced analog circuit specialists. On account of the above reasons, it has been desired to improve design methods of analog integrated circuits.Circuit-level synthesis method of CMOS operational amplifier(Op-Amp) is treated in this paper.Firstly, two methods are proposed to evaluate circuits' performance , which include simulation-based method and equation-based method. And a new topology synthesis method called "hierarchical decomposition + rule-based" is presented in this paper: a base for the CMOS Op-Amp including 24 valid topologies is produced according to hierarchical decomposition method; and according to rule-based method, an optimal topology is selected from the base during the course of devices sizing optimization.Secondly, the method of quasi-exactness penalization function is used to produce cost function which can be regarded as fitness function in improved adaptive genetic algorithm(IAGA). Thus, circuit-level synthesis of analog integrated problem can be converted into an unconstrained maximization problem.Thirdly, based on two mathematical algorithms including simulated annealing algorithm(SAA) and genetic algorithm(GA) are analyzed and compared in detail, IAGA is presented in this paper. It has prominent merits in computational cost and global convergence aspects.Finally, it has demonstrated that an CMOS Op-Amp meeting the requirements can be designed by way of the circuit-level synthesis method.