A Research And Design On Some Key Techniques In Conditional Access System Of Digital TV

With the development of digital technique, multimedia technique and network technique, broadcasting television is faced with a new opportunity. On the digital broadcasting television network, we could realize not only the traditional television service, but also a lot of new additional services, such as VOD, PPV, online games and data broadcasting. For implementing of these services, one key question is selecting a secure, open conditional access system.This thesis researches on some key technology of conditional access system. The main content is as follows:Firstly, the application background and development situation of CA system in china are briefly summarized; the syntax structure of PSI/SI message and interrelated DVB standard are analyzed; the composition and theory of CA are expatiated.Secondly, we research on the structure of CA system. According to the essential task of the CA system, we design the basic scheme of scrambling and descrambling, and describe the generating, handing out and pick-up of ECM and EMM message. We also discuss the implement of the conditional access module in set-top-box.Thirdly, based on some existing key distribution schemes, we discuss the key distribution strategy of the CA system, and propose a dynamic key distribution scheme which adapts to the situation of our country. The key distribution scheme solves the question of poor actual time performance and low distribution efficiency. This work has some innovation and high application value.In the end, we research and practically implement some encryption algorithms of the conditional access. DES algorithm and RSA algorithm are two representative algorithms. In this thesis, we describe the mechanism of DES in detail; based on the iterative trait of DES grouping cipher, we discuss the question how to use FPGA to complete high-speed implementation of algorithm. And we propose the method about the creation of subkey, design of Sbox, design of pipeline and subkey delay control. In this thesis, we also introduce the implementation flow of RSA and the method of generating big prime and key, and simulate the method of big prime and key with C language. The key of RSA is the modular exponentiation multiplication of large number, in this thesis, we modify the Montgomery algorithm which be used to implement RSA. We implement DES algorithm and 1024-bit RSA algorithm with Verilog HDL, and simulate their FPGA implementation with Modisim synthesis tool. Finally we test the correctness and performance of the implementation method.