Research And Development Of Dummy Experiment Software Of The Single Chip Microcomputer Based On VB

The teaching of single chip microcomputer must be combined with the experiment. But during the experiment teaching, the problem that the hardware simulations of single chip microcomputer go out of work often happens. Therefore, the dummy experiment software of the single chip microcomputer which is based on VB and Windows is developed in this thesis to avoid it for the students who are studying in the university. This software could realize the injunction simulation and function estate simulation on the ordinary computer, and incorporated program, modification, function, etc. This virtual system dosen't need any hardware invest. The experimenter can make experiments on any computer.This thesis introduces the composing and function of the software which is introduced by the idiographic examples firstly. The function of it includes the program edition, program function and result view. In the first part the assemble language is edited and then it comes into being a file. In the second part the assemble language program selected is run according to some simple hardware. There are two kinds of the function. One is series and the other is step. The user can view every memorizer during the function. For some appointed hardware the output can be seen.Secondly, the principle of discrete-system simulation was introduced, and the method of the simulating procedure was discussed in details. The method of course interactive is adopted to realize the simulation and push the simulation timer in order to make the time and step of the simulation run orderly. In this part the method which is formed with structure and object-oriented is adopted based on the design method.In the last part which is the main part of this thesis, the design of process is illuminated. And the structure of this software is introduced in details. It includes program edition, assemble language function and memorizer view modules. Each module is divided into several sub-modules. The simulation of timer interrupt and the data files are illuminated.