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The Backward Design Of Digital Vernier Caliper Circuit

Posted on:2007-06-05Degree:MasterType:Thesis
Country:ChinaCandidate:Y J GengFull Text:PDF
GTID:2178360182999948Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Digital vernier caliper is composed of capacitance grid transducer, Liquid Crystal Display and corresponding testing circuit. Capacitance grid transducer transform the displacement into capacitance'change, the testing circuit transform the capacitance'change into Alternating Current signal's phasic change, so test the signal's phasic change, the displacement is got. The scale of digital vernier caliper's circuit is comparatively large, approximately 40,000 transistors. This test mainly discuss parts of circuit, including the clock chain's circuit, the eight mutually drive's circuit and the manifestation drive's circuit. This task adopt the backward design method, begin with original chip's layout, pass through connecting photos, label, sort, distilling circuit and verification, lastly complete the layout which anew designed.The original chip adopt technics of P trap, CMOS, 3 μ m, one layer of aluminium, one layer of polycrystalline silicon. After distilling the circuit, the elements of the circuit be analysed. The eight mutually drive bring eight Alternating Current signals which phasic discrepancy of π/4 in turn, and transmit these eight signals to the eight emission flake in every flake team in capacitance grid transducer. The output of capacitance grid transducer and the testing displacement share pro rata. The clock chain's circuit bring signals which correspond to the work of all the circuit in scheduling and function. The manifestation drive connect Liquid Crystal Display, the testing data of the circuit is displayed in digital signals which provide convenience for the read and control.The verification of the circuit adopt the Cadence company's Verilog-XL. Every part circuit's verification result show that the circuit of distilled is right. The anew designed layout adopt technics of P trap, CMOS, 0.8 μ m. Put up Design Rule Check, Layout-vs.-Schematic, Electric Rule Check and so on for the new layout, no error, it should be right.
Keywords/Search Tags:Digital vernier caliper, Capacitance grid transducer, clock chain, eight mutually drive, manifestation drive
PDF Full Text Request
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