Vperl Extension And Improvement Research

As IC design scale becomes larger and larger, how to improve front-end design efficiency becomes a critical problem. Vperl can eliminate the Verilog redundancy, through automatic IO port deducing, automatic sensitivity list completion and automatic inter-module wire connect, greatly improve RTL design efficiency.But Vperl also has number of drawbacks in practial usage. This paper describes a new implementation Vperl2 using lexical analysis approach based on Vperl, which has overcome the incapability of analysis recursive concatenation struct and incapability to specify destination file directory. By disk IO operation minimization and design parsing information cacheing, Vperl2 has large improvement on parsing performance and flexibility.This paper then analysis the redundant information in Verilog RTL design, introducing a new Vperl2 syntax for FSM design automation. This paper briefly introduced conception on lexical analysis, then describe Vperl2 source code scan and signal extaction and procession algorithm in detail, and by reasonably merging greately reduced disk operation during source code parsing;optimize submodule interwire automation algorithm by using Berkeyly Database to store module IO port information, which reduce both file parsing and disk IO load. This paper uses a practical design to illustrate how remarkable Vperl works and give a Vperl2 and Vperl performance comparison. Finally this document draws a fair conclusion about Vperl2's advantage, disadvantage and its roadmap.