A Design Of Digital Image Algorithm Evaluation System & KLT Tracker Research

The real-time digital image processing systems presented is based on DSP + FPGA +USB2.0 architecture. The USB 2.0 interface with FPGA can reliably supply various modes of image data from PC to the image-processing module with high speed. And main image processing module uses high-performance DSP (TMS320C6202B) and Xilinx Spartan-IIE FPGA to realize the real-time digital image process algorithm, in the same time uses large-scaled programmable logical array CPLD to control and glue logic. Various digital image process algorithms are realized and pipeline construction are discussed in the field programmable gate array chip using VHDL language, such as morph filters,median filter,convolution filter,image segmentation plus rand order filter. The whole system is digital that superior than the analog video signal. It proved to be a reliable and effective for the request of system basically. Background affine model parameters estimation is a key problem in image registration between frames. This paper proposes to use extended Kanade-Lucas tracker and RANSAC algorithm to solve the background affine model parameters. Features belonged to background are detected using outlier voting frame. As solving an affine model only need three corresponding points, the algorithm can run in real time and generate reliable results.