MPU Design Of The Digital Visual Interface

I designed and verified a embedded LME_C51 MPU IP core. This MPU applied inthe DVI(Digital Visual Interface) project. Through the maintenance of the I2C bus,this MPU can transfer information such as identity verification between TMDStransmitter and TMDS receiver. The architecture of LME_C51 MPU belongs to theHavard structure type,which means that the program memory and the data memorywork independently. LME_C51 MPU has two stage pipeline. The first stage is calledthe instruction fetching and decoding stage. The second stage is called the calculationand writing back stage. The two stages work independently to accelerate the MPUspeed, so that most instructions (not including jump ones) can complete in one clockperiod. The total structure of LME_C51 MPU is comprised of 4 parts such asinstruction memory part,data memory part,interface part and execution part. It hasvarious instructions and addressing mode. It has plenty of resources such ascounter/timer,uart,parallel port and interruption working method. LME_C51 MPUcan fulfill complicated calculation and control. It can be embedded into various ASICas a IP core and provide strong support for various digital system design. I designed a I2C EEPROM virtual device. This device can write continuous Nbytes data,which comes from the master device of the I2C bus, into the EEPROMstorage unit according to the I2C writing time specification. It can read continuous Nbytes data from the EEPROM storage unit to the SDA bus according to the I2Creading time specification. I2C EEPROM can simulate the slave device of the I2C busto receive the control of LME_C51 MPU. When we connected the LME_C51 MPUwhich has I2C bus control instructions inside its internal ROM to the I2C EEPROMand simulated the test with Modelsim or Ncverilog Software,the result revealed thatLME_C51 MPU can manipulate the I2C bus properly. According to the possible LME_C51 MPU working conditions,I implemented thesimulation verification and FPGA verification on the LME_C51 MPU. I designedvarious test programs with KEIL C51 software, such as the instruction test program,the counter/timer test program,uart test program ,parallel port test program,interruption test program and etc. The test programs were converted into thesynthesizable LME_C51 MPU internal ROM and simulated. The simulation result ofthe various tests mentioned above is OK. With FPGA platform,I synthesized,mapped, implemented the LME_C51 MPU and assigned package pin of it so that Ican fulfill the FPGA verification on it. The FPGA verification result of the varioustests mentioned above is OKAll test, simulation and FPGA verification result proved the LME_C51 MPUand I2C EEPROM to be successful designs.