Design And Implementation Of A TDNLMS Adaptive Filter For Small Object Detection

Real-time small targets detection in digital image is one of the research focus in image processing. With the progress of VLSI (Very Large Scale Integration) technology and EDA (Electronic Design Automatic) technology, ASIC(Application Specific Integrated Circuit) provide a hardware platform for real-time detection. The adaptive filter based on TDNLMS(Two Dimension Normal Least Mean Square) algorithm can suppress complex background, has high performance of detection, simple structure and easy to hardware implementation. With the research of TDNLMS algorithm, the architecture of the adaptive filter can be divided into four modules in according to function: memory module, filter module, adaptive module and control module. The memory module is used to store the data of image with the wide of 128,256,512 pels; the filter module perform convolution of image data and weight, and it is a transversal filter; the adaptive module updates the weight matrix, and its structure is designed in according to the formula direct; under the control of the control module, the filter can work in four states which are standby, programming, initiation and filter with pipeline or without pipeline. The tap matrix is a key part of the adaptive filter , each tap is make up of multiplier, adder, registers, and multiplexers, it can export different result in different step of iteration and can work in standby, working or reference states to realize various type of filter's support region. Simplified algorithm and its pipeline architecture is provided to improve the throughput and the effect of transformation on filter's performance is discussed by experiment, the result shows that the performance of simplified algorithm is worse than standard algorithm, and pipeline's is more worse, but the application of pipeline can prove the working frequency greatly. The pipeline with step-size parameter near the region from 2-9 to 2-4 can satisfy detection performance. The RTL (Register Transfer Level)design is accomplished by Veirlog hardware description language, and synthesized with the standard cell library of SMIC 0.18um. The working frequency of the adaptive filter is 50MHz.