Study Of Software Defined Radio Processor For MIMO-OFDM System

Currently, The wireless base station's function is excessively lean upon accelerating components, which makes the structure of processor inflexible and difficult to upgrade. Software-defined radio which implements radio functions in software, with good flexibility and scalability, is considered to be a solution that meets the future development trend. As the key techniques with great computing complexity in 4G communication, FIR filter, DFT, channel estimation and MIMO channel equalization have good parallelism and some special operational modes, which make the adoption of specialized instructions and structures possible in the processor level. In this paper, a SDR processor prototype was proposed for MIMO-OFDM system which provide the foundation for furture study of soft base station platform.This text carried on a thorough study to the existing SDR architecture and base station platform first, then analyzed the advantage and shortage of these SDR processors. Based on the analysis of the existing architectures, this paper summarized some possible trends for SDR technique in the future. Meanwhile, this paper first discussed the principles and methods of OFDM, MIMO, channel estimation and channel equalization, and analyzed their complexity and operational characteristic, then present one kind of SDR processor prototype based on VLIW+SIMD architecture. The proposed architecture contains some data processing units and a lot of specialized instructions orienting to the application. The main work of the thesis is concentrating on analyzing the technical principle and complexity of the key technique possiblely adopted by future 4G and completing the detailed design of instruction system and function parts of processor. By using LISA language, a clock-cycle accurate processor model and its assembler,linker is built. Finally, three typical algorithm FIR filter, FFT and matrix multiplication were maped to the processor simulator, and the simulation resurts were compared with C64x+ processor, the highest speedup rate for FIR filter, FFT, 2*2 and 4*4 matrix multiplication were 7.95, 8.66, 11.2 and 12.6. It shows that the proposed processor is fit for application.