Research On Coherent Pulse Train Digital Receiver On Hardware

The article presents an introduction of algorithm for every module of coherent signal digital receiver, including IQ conversion, signal detecting, signal identifying, and coherent signal frequence estimation. The algorithm of coherent pulse train frequence estimation is discussed in detail, furthermore a series of optimization methods are used to improve the efficiency of hardware system based on ADSP TS201 and FPGA XC5VSX95T.The algorithm of coherent pulse train frequence estimation is a high accurate frequency estimation method with coherency. The frequencies of all monopulse signals were estimated respectively, and the mean value of these estimates was considered as a reference frequency to down-conversion the coherent pulse train. All of the baseband signals were accumulated in intrapulse and a sinusoidal signal was acquired, of which the frequency is the difference between the carrier and the reference frequencies, the duration is the pulse train duration and the signal-to-noise ratio(SNR) is N times that of the SNRin. Accordingly, it is possible to get high accurate frequency estimate of the sinusoid. Then the frequency of coherent pulse train was obtained by the reference frequency plus the difference.An algorithm about unifying TOA (time of arrival) of pulse was addressed for the coherent linear frequency modulation signal which is discussed in detail in the paper. According to the character of the LFM, namely, the frequency estimated error is proportional to the TOA estimated error, so we can modify the TOA of other pulses based on maximal (minimum) frequency if the FM slope is positive(negateve).And then we can estimate the Doppler frequency offset between the first half and the second half of the whole coherent pulse train. The paper has demonstrated the operation of concrete steps, and the simulation exam has already proved that the algorithm's validity, Moveover, as the coherent pulse train frequence estimation algorithm needs coherent plus phase of each pulse, however the environment is changing and complicated, the coherence of the pulse train is not good enough, usually there are some inflexions, that is between the next two inflexions the coherence of this part is well enough, while the coherence of the whole pulse train are damaged. The paper has presented a plus coefficient part linear regression on the signal phase which can settle the problem.The paper has also discussed the software and hardware implementation of coherent signal digital receiver, the operation of concrete steps has been demonstrated. While refer to program design, an impressive program criterion and methods on how to increase processing rate is presented. When memory allocating, buser need to be properly assigned to decrease bus conflicts; datas that used at the same time should better put into different memory blocks. After optimization, the result of the operation of this DSP and FPGA system indicated that the work is effective and coincide with the project requirements.