Design And Realization Of Echo Cancellation System For RF Repeaters In Single Frequency Networks

Along with the rapidly developing of mobile communication today, there are some problems. No matter what kind of wireless communication, the weak signal areas and the blind spots still existing in the covered regions. Repeater effectively enlarge the cover areas in remote areas and somewhere there are not so many users. It can filter and enlarge the land digital signals and cover the weak signal areas and the blind spots effectively, it also has some benefits of flexible realization, rapid construction, and reasonable cost control.The signal transition mode of repeater which works on the same frequency has some troubles on signal coupling between receive and transmit aerials, the signal from transmit aerial may leak out into receive aerial which have serious interference on transition signal. The usage of multi-path interferences cancellation technology makes the goal of reasonable isolation easy to achieve, even does not use the method of physical isolation, which also lower the system cost and faster the process of development.The paper designs the plan of interference cancellation system which firstly uses CAZAC code as the method of initial channel estimation, secondly uses Step-changeable LMS arithmetic to track the change of the channel. Then, makes the simulation of system plan which uses digital tv signal (DVB-T) as the source of simulation.The hardware plan, based on the software radio theory, uses DSP and FPGA as the main part of function realization, which forms the platform of digital intermediate frequency system. As the flexibleness of software radio theory, the platform has common usage on broadcast system, mobile communication system as CDMA, 3G standards such as WCDMA, TD-SCDMA, CDMA2000 and so on.The realization of system software divides into two parts: FPGA system and DSP system. There are three parts in FPGA: signal chain control module, initial channel estimation module and control module of adaptive arithmetic. The designs of DSP system include boot-load module, FLASH SDRAM control module and data exchange module between DSP and FPGA. At last system adaptive arithmetic is tested in hardware platform, and the result proves the function of system arithmetic has been achieved.